1. Field of the Invention
The present invention relates to memory control circuits provided with an instruction pre-fetch function, for controlling the reading of instructions to be fetched by the Central Processing Unit (CPU), from a memory and microprocessor systems that include the memory control circuits, and particularly to a memory control circuit and a microprocessor system both having a reduced penalty-cycle occurrence rate during the execution of branch instructions.
2. Description of the Related Art
It has been conventionally known in microprocessor systems which use pipeline control that instruction data is read in advance from a main memory and buffered by an instruction pre-fetch function so as not to stagnate the flow of instructions to a CPU. In such a system, however, if an instruction branch occurs, instruction data read in advance by a pre-fetch cannot be used, the pre-fetch buffer is cleared, and the branch-destination instruction needs to be fetched. Therefore, until new data reaches the CPU, the flow of the pipeline stops, and processing performance is reduced.
To solve this issue, conventionally, an instruction cache memory which can be accessed at high speed is prepared and when the cache memory has the branch-destination instruction, the instruction is executed without any penalty cycle. In this case, however, if the branch-destination instruction is not cached, the instruction needs to be fetched. Therefore, the pipeline flow is stopped, and processing performance is reduced. To increase the hit rate of the instruction cache memory, the data capacity of the instruction cache memory needs to be made larger, which increases the circuit size and manufacturing cost.
There has been a microprocessor system (disclosed, for example, in paragraphs No. 0008 to No. 0011 and FIG. 1 in Japanese Unexamined Patent Publication No. 9-305490 (1997)) in which a counter is provided between a CPU and an instruction cache memory and has the number of instruction cache entries as its initial value, the counter is decremented every time an access is made to the instruction cache memory, the counter is initialized every time when a subroutine call occurs, or a branch is generated in the address negative direction, and the counter function is stopped when the instruction cache memory becomes full of data. This structure increases the hit rate of the instruction cache memory, obtained when a subroutine call occurs, or a branch is executed in the address negative direction.
In the conventional related art, there has been an instruction pre-fetch method (disclosed, for example, in paragraphs No. 0016 to No. 0020 and FIG. 1 of Japanese Unexamined Patent Publication No. 5-216665 (1993)) in which a buffer storage, an instruction pre-fetch circuit, and an instruction buffer are provided between a main memory unit and a CPU, a determination circuit determines whether a block transmitted to the buffer storage due to an instruction pre-fetch request includes a branch-destination instruction, and control is made according to the result of determination such that the instruction pre-fetch request is enabled or canceled.
In the microprocessor system disclosed in Japanese Unexamined Patent Publication No. 9-305490 (1997), described above, since the counter for counting the number of times the instruction cache memory is used is provided, the circuit size and manufacturing cost are increased. When the number of entries in the instruction cache memory is made larger, the hit rate of the instruction cache memory is increased during the execution of branch instructions. In this case, however, the size of the circuit which includes the instruction cache memory and the counter and manufacturing cost are increased.